Content Addressable Memories (CAMs) are commonly used in cache systems, and other address translation systems, of high speed computing systems. They are also useful in high-speed network routers, and many other applications known in the art of computing.
Each CAM typically has a CAM block array that includes a plurality of rows, each row has multiple CAM blocks and each CAM block has a plurality of CAM cells. The CAM cells are characterized by circuitry capable of generating a match output for each row of CAM blocks in the CAM block array thereby indicating whether any location of the array contains a data pattern that matches a query input and the identity of that location. Each CAM cell typically has the ability to store a unit of data, and the ability to compare that unit of data with a unit of a query input. Each CAM block has the ability to generate a match output. A compare result indication of each CAM block in a row is combined to produce a match signal for the row to indicate whether the row of CAM cells contains a stored word matching a query input. The match signals from each row in the CAM block array together constitute match output signals of the array; these signals may be encoded to generate the addresses of matched locations or used to select data from rows of additional memory.
Each CAM cell in each column is typically connected to a common read/write bit line and a search bit line. The common read/write bit line is used to write the data to a pair of memory cells, which can be part of a ternary CAM (TCAM) cell or a single memory cell, such as a binary CAM. Each memory cell is accessed using a word line which is decoded using an input address. The common read/write bit line is also used for reading the data from a memory cell. The differential developed across the read/write bit lines are sensed using a sense amplifier during a read cycle.
Further, each CAM cell in each column is typically connected to a common query data line, also referred to as a common search data line. The common search data line enables simultaneous data searching in each CAM cell in a column from a query input. The common search data line can also be used as a write data line, when the CAM cell is based on a PMOS compare circuit.
The unit of data that is stored in a CAM cell is often binary, having two possible states: logic one, and logic zero. The CAM blocks of these arrays produce a match compare result if the query input is equal to the data stored in the CAM cells in the CAM blocks, and a mismatch result if otherwise, whereas the TCAM cells can store three states: logic one, logic zero, and don't care. TCAM blocks of these TCAM cells produce a local match compare result if the query input is equal to the data stored in the TCAM cells in the TCAM blocks, the query input contains a don't care state, or the data stored is a don't care data. The TCAM cells produce a mismatch result otherwise. The TCAM cells are particularly useful in address translation systems that allow variable sized allocation units.
Typically, the current TCAM cells require a significantly large silicon area, which can result in consuming more power. One conventional technique to reduce the silicon area and power consumption uses NAND based compare circuits to reduce the TCAM cell size and power consumption. However, this technique fails to perform well at lower voltages, because the voltage at the gate of the TCAM cell is equal to VDD (supply voltage)−Vt (threshold voltage), and limits system performance.
Another conventional technique uses same bit lines that are used for read/write as well as search to reduce the number of total bit lines per TCAM cell in an effort to reduce the silicon area. This approach requires using PMOS transistors in the compare circuit, which generally reduces the speed of operation during a compare operation. In addition, this approach requires evaluating the search bit lines during write operation, which results in the dissipation of a large amount of power. In addition, this approach increases capacitance (parasitic effects between bit lines), which can result in considerably reducing the TCAM cell performance.